This invention relates generally to level shifter circuitry and more particularly, it relates to a gate oxide protected level shifter which has a higher speed of operation than is traditionally available.
As is generally well-known, digital logic circuits are widely used in the areas of electronics and computer-type equipment. However, the various digital logic circuits that must communicate with one another may have different power supply voltages. For example, a first circuit that operates with logic levels between 0V (L) and 2.0V (H) may need to communicate with a second circuit that operates with logic levels between 0V (L) and 3.3V (H). Thus, when a first digital logic circuit of one power supply voltage is required to interface with a second digital logic circuit of another power supply voltage there is typically needed a voltage conversion or translation between the two different power supplies so that they will be compatible with each other and not drain static current. A level shifter circuit is provided to perform this function.
In FIG. 1, there is shown a schematic circuit diagram of a prior art level shifter 2 which may be used for performing a voltage conversion. The level shifter 2 is comprised of a pair of cross-coupled P-channel MOS transistors P1 and P2, a pair of input N-channel MOS transistors N1 and N2, and a CMOS inverter I1. The first P-channel transistor P1 has its source connected to an upper predetermined I/O buffer power supply voltage VDDIO, which is typically at +3.3 volts, and its drain connected to the drain of the first N-channel transistor N1 and to the gate of the second P-channel transistor P2. The gate of the first P-channel transistor P1 is connected to the drain of the second P-channel transistor P2 and to the output terminal OUT. The second P-channel transistor P2 has its source also connected to the power supply voltage VDDIO. The drain of the transistor P2 is connected also to the output terminal OUT and to the drain of the second N-channel transistor N2. The gate of the transistor P2 is connected to the drain of the transistor P1 and to the drain of the transistor N1.
The gate of the first N-channel transistor N1 is connected to an input terminal IN for receiving an input signal and to the input of the inverter I1. The output of the inverter I1 is connected to the gate of the second N-channel transistor N2. The sources of the N-channel transistors N1 and N2 are connected to a lower predetermined or reference power supply voltage VSSIO (ground) or 0 volts. The CMOS inverter is conventional and is formed of a P-channel transistor and an N-channel transistor whose gates are connected together defining its input and whose drains are connected together defining its output. The source of the P-channel inverter transistor is connected to a supply potential VDD. The p-type substrate of the N-channel transistors N1, N2 is tied to ground, and the n-type substrate of the P-channel transistors P1, P2 is tied to the power supply voltage VDDIO.
In operation, when then input signal at the input terminal IN is at 0 volts the transistors N1 and P2 will both be turned OFF and the transistors N2 and P1 will be turned ON. As a result, the level shifter 2 will produce a voltage level of 0 volts at the output terminal OUT. On the other hand, when the input signal at the input terminal IN is at 2.0 volts, the transistors N1 and P2 will both be turned ON and the transistors N2 and P1 will be turned OFF. Thus, the level shifter 2 will provide a voltage level of +3.3 volts at the output terminal OUT.
However, in view of the developments made in CMOS technologies the thickness of the transistor gate oxides for forming the CMOS transistor devices are becoming thinner and thinner. In the typical semiconductor process, where the thickness of the gate oxide is reduced to approximately 60 .ANG. (angstrom) or below a voltage difference higher than about +2.4 volts-+2.5 volts applied across the gate and the bulk of the transistor devices will cause a breakdown in the gate oxide to occur, thereby resulting in a failure. For example, when the input signal of 0 V is applied to the gate of the first input N-channel transistor N1 the level shifter 2 of FIG. 1 will generate a voltage level of 0 V at the output terminal OUT. As can be seen, a voltage difference of 3.3 V will exist between the drains and the gates of the P-channel transistors P1, P2. Therefore, if the gate oxide thickness is equal to or lower than 60 .ANG. the gate oxide will experience a breakdown and the level shifter 2 will fail. In order to overcome this problem, there have been provided in the prior art gate oxide protected level shifter circuits utilizing a plurality of PMOS and NMOS transistors so as to limit the voltage difference at the gate oxide to be below a breakdown voltage magnitude.
In FIG. 2, there is illustrated a schematic circuit diagram of a prior art gate oxide protected level shifter 4. The level shifter 4 is also comprised of a pair of cross-coupled P-channel MOS transistors P1, P2; a pair of input N-channel transistors N1, N2; and a CMOS inverter I1 which are identical to the components in the level shifter 2 of FIG. 1. In addition to these components, the level shifter 4 of FIG. 2 further includes PMOS transistors P3, P4 and NMOS transistors N3, N4 which function to prevent the gate oxide voltage of any transistor from exceeding a breakdown voltage. If the thickness of the gate oxides is assumed to be approximately 60 .ANG., then the voltage difference at any gate oxide of the level shifter 4 will not exceed approximately +2.5 V.
The PMOS transistor P3 and the NMOS transistor N3 are connected together in series and between the drain of the transistor P1 (node S1) and the drain of the transistor N1 (node S2). Similarly, the PMOS transistor P4 and the NMOS transistor N4 are connected together in series and between the drain of the transistor P2 (node S3) and the drain of the transistor N2 (node S4). The gates of the transistors P3, P4 are connected to a PMOS reference voltage VREF11, and the gates of the transistors N3, N4 are connected to an NMOS reference voltage VREF22. The reference voltages REF22 and REF11 can be generated by a reference voltage generation circuit which is illustrated and described in detail in co-pending application Ser. No. 08/861,039 filed on May 21, 1997 entitled "Reference Voltage Generation Scheme for Gate Oxide Protected Circuits" and assigned to the same assignee as the present invention.
It is assumed that the upper predetermined I/O buffer power supply voltage VDDIO is on the order of +3.3 V and the lower predetermined power supply voltage VSSIO is on the order of 0 V. Further, the reference voltage VREF22 is approximately +2.2 V and the reference voltage VREF11 is approximately +1.1 V. The supply potential VDD is on the order of +2.0 volts. It will be noted that there is required a predetermined amount of time for the input signal on the input terminal IN to switch from an initial voltage level of +2.0 V (or 0 V) to a final voltage level of 0 V (or +2.0 V). In response to this switching operation on the input terminal, there will be required a predetermined amount of time for the pper non-inverted output signal OUT.sub.-- LSP and the upper inverted output signal OUTB.sub.-- LSP at the respective nodes S3 and S1 to switch from an initial voltage level of VDDIO (or VREF11+.vertline.V.sub.tp .vertline.) and a final voltage of VREF11+.vertline.V.sub.tp .vertline. (or VDDIO). Likewise, there will be required a predetermined amount of time for the lower non-inverted output signal OUT.sub.-- LSN and the lower inverted output signal OUTB.sub.-- LSN at the respective nodes S4 and S2 to switch from an initial voltage of VREF22-V.sub.tn (or VSSIO) and a final voltage of VSSIO (or VREF22-V.sub.tn).
The level shifter 4 suffers from the disadvantage that it takes a relatively long time for the nodes S1 and S3 to switch between its initial voltages and its final voltages in response to the switching of the input signal. This is due to the fact that the nodes S1 and S3 are required to be pulled down through three transistors. For example, the node S1 is serially connected to the transistors P3, N3 and N1. Similarly, the node S3 is serially connected to the transistors P4, N4 and N2. In view of this, it can therefore take a relatively long period of time for the gates of the transistors P1 and P3 to resolve their "full" logic levels of VDDIO (H) and VREF11+.vertline.V.sub.tp .vertline. (L).
The inventors of the present invention have developed a way of increasing the switching speeds at the gates of the transistors P1 and P3 (nodes S1 and S3) in the level shifter 4 of FIG. 2. This is achieved by modifying the level shifter 2 so as to include first and second capacitors operatively interconnected for speeding up transitions at the gate of the transistors P1 and P2.